+ Add to collection

CURATOR

EXTRAS

  • Lifetime access. No limits!
  • Mobile accessibility
  • Add to wishlist

Computer-Design Verification & Test of Digital VLSI Circuits

+ Add to collection

Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT Guwahati. For more details on NPTEL visit http://nptel.iitm.ac.in

Self-Study Content
  1. Mod-01 Lec-01 Introduction to Digital VLSI Design Flow

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  2. Mod-01 Lec-02 High Level Design Representation

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  3. Mod-01 Lec-03 Transformations for High Level Synthesis

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  4. Mod-02 Lec-01 Introduction to HLS: Scheduling, Allocation and Binding Problem

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  5. Mod-02 Lec-02 Scheduling Algorithms-1

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  6. Mod-02 Lec-03 Scheduling Algorithms-2

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  7. Mod-02 Lec-04 Binding and Allocation Algorithms

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  8. Mod-03 Lec-01 Two level Boolean Logic Synthesis-1

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  9. Mod-03 Lec-02 Two level Boolean Logic Synthesis-2

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  10. Mod-03 Lec-03 Two level Boolean Logic Synthesis-3

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  11. Mod-03 Lec-04 Heuristic Minimization of Two-Level Circuits

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  12. Mod-03 Lec-05 Finite State Machine Synthesis

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  13. Mod-03 Lec-06 Multilevel Implementation

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  14. Mod-04 Lec-01 Introduction to formal methods for design verification

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  15. Mod-04 Lec-02 Temporal Logic: Introduction and Basic Operators

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  16. Mod-04 Lec-03 Syntax and Semantics of CTL

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  17. Mod-04 Lec-04 Syntax and Semantics of CTL -- Continued

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  18. Mod-04 Lec-05 Equivalence between CTL Formulas

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  19. Mod-05 Lec-01 Introduction to Model Checking

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  20. Mod-05 Lec-02 Model Checking Algorithms I

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  21. Mod-05 Lec-03 Model Checking Algorithms II

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  22. Mod-05 Lec-04 Model Checking with Fairness

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  23. Mod-06 Lec-01 Binary Decision Diagram: Introduction and construction

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  24. Mod-06 Lec-02 Ordered Binary Decision Diagram

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  25. Mod-06 Lec-03 Operation on Ordered Binary Decision Diagram

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  26. Mod-06 Lec-04 Ordered Binary Decision Diagram for State Transition Systems

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  27. Mod-06 Lec-05 Symbolic Model Checking

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  28. Mod-07 Lec-01 Introduction to Digital VLSI Testing

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  29. Mod-07 Lec-02 Functional and Structural Testing

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  30. Mod-07 Lec-03 Fault Equivalence

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  31. Mod-08 Lec-01 Fault Simulation-1

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  32. Mod-08 Lec-02 Fault Simulation-2

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  33. Mod-08 Lec-03 Fault Simulation-3

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  34. Mod-08 Lec-04 Testability Measures (SCOAP)

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  35. Mod-09 Lec-01 Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  36. Mod-09 Lec-02 D-Algorithm-1

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  37. Mod-09 Lec-03 D-Algorithm-2

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  38. Mod-10 Lec-01 ATPG for Synchronous Sequential Circuits

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  39. Mod-10 Lec-02 Scan Chain based Sequential Circuit Testing-1

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

  40. Mod-10 Lec-03 Scan Chain based Sequential Circuit Testing-2

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Bisw

Show More
Reviews

Ask your own question. Don't worry, it's completely free!